Virtex UltraScale+ devices offer the finest performance and combination competences in a FinFET node with a 14nm or 16nm manufacturing node. For the most demanding design needs, the 3rd generation Xilinx 3D ICs employ stacked silicon interconnect (SSI) technology to deliver maximum signal processing and serial I/O bandwidth. A virtual monolithic design experience may be offered because to the registered inter-die routing links, which enable >600 MHz operation and abundant and customizable clocking.
It is critical to pre-process data before executing it on fixed-function computing systems in order to achieve the best results. Manufacturer claims that the VU57P FPGA, which features adaptive logic and 460GB/s of HBM bandwidth, can choose data, convert and groom it to optimise the inputs for the target accelerator. Throughput and system performance are improved while power consumption is reduced using the xilinx virtex ultrascale plus VU57P FPGA’s high-speed 58G PAM4 transceivers.
Switches and routers with QoS capabilities
Nx400G/200G/100G/50G switch with a 400G datapath pipeline and traffic control for quality of service may be supported using 16G HBM on the Virtex UltraScale+ VU57P FPGA with 16G HBM. 58G PAM4 transceivers provide connectivity to the most contemporary optical standards, double the transmission rate between the primary switching function and the transceiver. Packet categorization, switch and route look-up tables, and traffic control queues for the switch are all used to achieve high-bandwidth switching. As a consequence of the power and thermal restrictions, Virtex UltraScale+ VU57P FPGA-based switches and routers may adopt a less complicated cooling mechanism while giving higher performance through lidless packaging choices, which is vital to data centre and telecom infrastructure deployments.
When it comes to small form factor applications, only Artix UltraScale+ FPGAs have integrated fan-out (InFO) packaging (9.5×11.5mm). These FPGAs with InFO packaging are 70% smaller and 70% thinner than chip-scale packaging, and they provide class leading compute density in terms of serial I/O bandwidth and DSP computing per mm2. As addition as distributing heat and power more evenly, inFO packing may also extend the flight durations and signal integrity of satellites.
The speed of serial I/O is critical
In networking, video, and vision applications, Artix UltraScale+ FPGAs are well-suited because of their transceivers’ 16Gb/s bandwidth. Among the supported standards are PCIe® Gen4, 10GE Vision, CoaXPress 2.1, and 12G-SDI. Power efficiency over seven series FPGAs and equalisation algorithms guarantee good signal integrity during transmission in the production-proven transceiver design.
Digital signal processing is referred to by the term “DSP Compute”
This is the most cutting-edge FPGA DSP architecture currently available in a cost-optimized device: Artix UltraScale+ DSP slices. They offer a broad variety of compute applications, including image and video processing, real-time control, wireless processing, and artificial intelligence inference, and are optimised for both fixed- and floating-point calculation. The DSP compute of the Artix-7 FPGAs and competing FPGAs in their class is more than doubled by the family compared to the previous generation.
Safety and security are crucial factors
Many levels of security safeguard Artix UltraScale+ FPGAs, guaranteeing the highest level of security and protection for intellectual property. In addition, the design features RSA-4096 verification, DPA countermeasures, NIST-certified AES-CGM decryption, anti-tamper configuration, and a security monitor IP that enables the architecture to familiarise as security threats change during the life cycle of the product.
The LVDS and MIPI Interfaces’ Performance
Camera sensor capture and display applications benefit greatly from Artix UltraScale+ FPGAs, which are only cost-enhanced FPGAs in the market that can provide up to 2.5Gb/s of MIPI performance. As an added bonus, this website provides direct access to a comprehensive MIPI IP and reference design solution.